CSC3050 Project 4: Cache Simulation
CSC3050 Teaching Group
November 20, 2024
1 Introduction
Cache is an important component of a CPU system that has a signiffcant impact on computer
performance by reducing memory access times. The focus of this project is to simulate the
cache in the RISC-V architecture to give you hands-on experience with the cache system
and its role in improving system performance.
2 Overview
This project is divided into three main parts:
1. Single-Level Cache Simulation: In this part, you are required to design and implement
 a cache simulator that enables the single-level cache simulation. Moreover,
you need to use the single-level cache simulator you implemented to compare the cache
performance under different cache parameters.
2. Multi-level Cache Simulation: In this part, based on the single-level cache simulator,
 you are required to further implement a multi-level cache simulator. You need
to examine further how a multi-level cache can improve performance compared to a
single-level cache.
3. Implementation of Pre-fetching: In this section, you are required to implement
a critical technique known as pre-fetching. Moreover, you need to compare the cache
performance with and without pre-fetching.
3 Single-Level Cache Simulation
• Implementation Requirements: You are required to implement a Cache class for
simulating a single-level cache (The code from [1] is a reference code for your). The
ffle structure and description you may use are shown in Table 1.
The simulated cache should be able to perform some parameter tuning, such as cache
size, block size, and associativity level. Besides that, you are required to simulate
1ffle name Discription
include/Cache.h Statement of the Cache class.
src/Cache.cpp Implementation of Cache class.
src/MainSinCache.cpp Main entrance of the single-level cache simulator.
src/MainMulCache.cpp Main entrance of the multi-level cache simulator.
Table 1: File structure and description of single-level and multi-level cache simulation.
Parameter Values
Cache Size 4KB to 1MB, incremented by 4X.
Block Size 32Bytes to 256Bytes incremented by 2X.
Associativity 2 to 32 incremented by 2X
Write Back True or False.
Write Allocate True of False.
Table 2: Parameters used in single-level cache simulation.
Write Back and Write Allocate policies using the LRU replacement algorithm in your
simulation. The parameters that are tunable and their ranges are listed in Table 2.
Finally, some performance data (e.g. miss rate of the cache and total access latency)
needs to be saved in a CSV ffle.
• Performance Evaluation: After the implementation, you are required to evaluate
the cache performance based on your simulator. We will provide you with a test trace
(test.trace) to facilitate the performance evaluation. What you can do includes but is
not limited to
– Analyzing the trend of Miss Rate with Block Size under different cache sizes
– Analyzing the change of Associativity with Miss Rate under different cache sizes
– Analyzing the amount of cache misses per thousand instructions under different
cache sizes
You are also free to design scenarios for performance evaluation as you wish. But
please analyze the performance in at least two different scenarios. You should provide
graphical or tabular data and conduct the analysis based on the data mentioned above.
The results and analysis should be given in your report.
4 Multi-Level Cache Simulation
• Implementation Requirements: You are required to simulate the multi-level cache
in this part based on your single-level cache simulator.
• Performance Evaluation: You should conduct the comparison between the singlelevel
 and multi-level cache system whose parameters are given in Table 3 and Table
4, respectively. The cache miss latency is set to 100 CPU cycles. Also, graphical or
2tabular data are required and you should put the comparisons and analysis in your
report.
Level Capacity Associativity Block Size Write Policy Hit Latency
L1 16 KB 1 way 64 Bytes Write Back 1 CPU Cycle
Table 3: Cache parameters for single-level cache.
Level Capacity Associativity Block Size Write Policy Hit Latency
L1 16 KB 1 way 64 Bytes Write Back 1 CPU Cycle
L2 128 KB 8 ways 64 Bytes Write Back 8 CPU Cycle
L3 2 MB 16 ways 64 Bytes Write Back 20 CPU Cycle
Table 4: Cache parameters for multi-level cache.
5 Pre-Fetching Implementation
• Implementation Requirements: Based on the multi-level cache simulation, you are
required to further add the pre-fetching technique. Specifically, the mechanism is to
prefetch data in advance based on a detected memory access pattern. In this project,
you will implement a pre-fetching algorithm capable of detecting fixed-stride memory
access patterns; the pseudo-code of the algorithm is summarized in Algorithm 1.
Algorithm 1 Stride-Based Pre-fetching Algorithm
1: initialize: stride = 0, is prefetch = false.
2: for Each Memory Access do
3: Calculate the memory access stride (the distance between the current memory access
address and the address of the previous memory access with the same operation).
4: if is prefetch = false and there are more than three times with the same stride then
5: is prefetch = true
6: prefetch address = current address + stride
7: Prefetching(prefetch address)
8: end if
9: if is prefetch = true and more than three times the different strides are detected
then
10: is prefetch = false.
11: Stop prefecting.
12: end if
13: end for
• Performance Evaluation: You are required to compare the performance of a multilevel
cache with and without pre-fetching. The setting of the multi-level cache is the
same as that in the previous part. Moreover, the test prefetch.trace is the test trace
3specifically designed for prefetching; you can do the performance comparison based on
it. The results should be included in your report.
6 Submission
For this project, you must use C/C++ to implement the cache simulator. If you use other
languages, you will get a 0 score. You need to submit the following files:
• src/*: include all source code files
• include/*: include all header files
• CMakelists.txt: the cmake file for your project
• project-report.pdf: a detailed description of your implementation. The specific things
that need to be included are as follows:
– The implementation details of your simulator.
– Performance evaluation and analysis mentioned above.
Please compress all files into a single zip file and submit it to the BlackBoard. The file name
should be your student ID, like 221019040.zip.
7 Grading Details
The overall score will be calculated as follows:
• Single-level cache simulation code: 20%
• Multi-level cache simulation code: 20%
• Pre-Fetching implementation code: 40%
• Report: 20%
For the code, we will check whether your code can run or not. Please make sure that your
code runs correctly. If the code does not run, it will be directly marked as 0 points.
8 About the reference code
To reduce the difficulty and complexity of implementation, we encourage you to refer to
existing code like [1]. This project is also designed based on [1]. However, if you simply
submit the code from the reference [1] or only do simple tasks like adding comments, we
consider that you haven’t put much effort and your grade will be directly marked as zero.
References
[1] Hao He, “RISCV-Simulator,” https://github.com/hehao98/RISCV-Simulator, 2019.
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